View STVM100DS6F_4123277.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STVM100
I2C LCD VCOM calibrator
Features

I2C interface, slave address: 1001111 7-bit adjustable sink current output 2.25V to 3.6V logic supply voltage VDD AVDD operating voltages - 4.5V to 20V for VDD from 2.6V to 3.6V - 4.5V to 13V for VDD from 2.25V to 3.6V EEPROM for storing the optimum VCOM setting Guaranteed monotonic output over operating range 400kHz maximum interface bus speed Operating temperature: -40C to 85C Available in an 8-pin 3mm x 3mm TDFN8 or 3mm x 3mm TSSOP8 Package TSSOP8 (3mm x 3mm) (DS) TDFN8 (3mm x 3mm) (DC)

Description
The STVM100 is a programmable VCOM adjustment solution for thin-film transistor (TFT) liquidcrystal displays (LCDs) to remove "flickers". It can replace a mechanical potentiometer, so that the factory operator can physically view the front screen when performing the VCOM adjustment. This significantly reduces labor costs, increases reliability, and enables automation. STVM100 provides a digital I2C interface to control the sink current output (IOUT). This output drives an external resistive voltage divider, which can then be applied to an external VCOM buffer. Three external resistors R1, R2, and RSET determine the highest and lowest value of the VCOM. An increase in the output sink current will lower the voltage on the external divider so that the VCOM can be adjusted by 128 steps within this range. Once the desired VCOM setting is achieved, it can be stored in the internal EEPROM that will be automatically recalled during each power-up. STVM100 is available in an 8-pin, 3mm x 3mm TDFN8 or 3mm x 3mm TSSOP8 package.
Applications
TFT-LCD panels
Table 1.
Device summary
Optimum temperature range -40C to 85C -40C to 85C Package TDFN TSSOP Packing ECOPACK package, tubes ECOPACK package, tape and reel
Order code STVM100DC6E STVM100DS6F
July 2007
Rev 6
1/27
www.st.com 1
Contents
STVM100
Contents
1 2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2-wire bus characteristics and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 2.3 2.4
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDD power supply ramp-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 4 5 6 7 8 9
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
STVM100
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Bit P read and write mode values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MLPD-DFN 3 x 3 x .75mm, pitch 0.65, package mechanical data . . . . . . . . . . . . . . . . . . . 23 TSSOP8 - 8-lead, thin shrink small outline, 3mm x 3mm, mech. data. . . . . . . . . . . . . . . . 24 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/27
List of figures
STVM100
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connections diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Read/write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 R1, R2, and RSET connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VDD supply current v's VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AVDD supply current v's AVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VDD supply current v's temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AVDD supply current v's temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 IOUT error v's temperature (STVM100 at middle scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Total unadjusted error v's DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Differential non-linearity v's DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Integral non-linearity v's DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AVDD power-up response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Full scale-up response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Full scale-down response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MLPD-DFN 3 x 3 x.75mm, pitch 0.65, package mechanical data . . . . . . . . . . . . . . . . . . . 23 TSSOP8 - 8-lead, thin shrink small outline, 3mm x 3mm, mech. data. . . . . . . . . . . . . . . . 24
4/27
STVM100
Device overview
1
Device overview
Figure 1. Logic diagram
VDD
SDA SCL WP STVM100
AVDD OUT SET
GND
AI12272
Table 2.
Name OUT AVDD
Pin names and functions
Type Analog Supply Function Adjustable sink current output pin. (1) See Section 3: Application information on page 11. High-voltage analog supply. Bypass to GND with a 0.1F capacitor. WRITE protectection. Active-low. To enable write operations to the DAC or to the EEPROM writing, connect to 0.7VDD or greater. Internally pulled down by a 130k resistor. Supply ground. Supply In/Out Input System power supply input. Bypass to GND with a 0.1F capacitor. I2C serial data input/output. I2C serial clock input. Maximum sink current adjustment point. Connect a resistor from SET to GND to set the maximum adjustable sink current of the OUT pin. The maximum adjustable sink current is equal to AVDD /20 divided by RSET (see Figure 4 on page 6).
WP
Input
GND VDD SDA SCL
SET
Analog
1. See SET pin function in this table for the maximum adjustable sink current setting.
5/27
Device overview Figure 2. Connections diagram
OUT AVDD WP GND 1 2 3 4 8 7 6 5 SET SCL SDA VDD
AI12273
STVM100
Figure 3.
Block diagram
VDD AVDD
19R
SDA SCL
I2C Interface
7 DAC
R
OUT + -
7
EEPROM Block
SET
WP GND
AI12274
Figure 4.
Hardware hookup
3.3V VDD
0.1F
AVDD
I2C Interface
VDD SDA AVDD R1
0.1F
MCU
STVM100 SCL WP GND OUT SET
+ R2 VCOM -
RSET
AI12275
6/27
STVM100
Device operation
2
Device operation
The STVM100 operates as a slave device on the serial bus. Access is obtained by implementing a Start condition, followed by the 7-bit slave address (1001111), and the eighth bit for READ/WRITE identification. The volatile DAC register and non-volatile EEPROM values can be read out or written in.
2.1
2-wire bus characteristics and conditions
This bus is intended for communication between different ICs. It consists of two lines:

a bi-directional data signal (SDA). a clock signal (SCL).
The SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocols have been defined:

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control signals.
2.1.1
Bus not busy
Both data and clock lines remain High.
2.1.2
Start data transfer
A change in the data line state from high-to-low while the clock is high indicate the Start condition.
2.1.3
Stop data transfer
A change in the data line state from low-to-high while the clock is high indicates the Stop condition.
7/27
Device operation
STVM100
2.1.4
Data valid
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is low (see Figure 5). The data on the line may be changed during the clock signal low period. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between the Start and Stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges transmission with a ninth bit. By definition, the device that gives out a message is called "transmitter", the device that gets the message is called "receiver". The device that controls the message is called the "master". The devices controlled by the master are called "slave" devices. Figure 5. Serial bus data transfer sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
8/27
STVM100
Device operation
2.1.5
Acknowledge
Each byte of eight bits is followed by one Acknowledge bit. This Acknowledge bit is a low level signal put on the bus by the receiver, whereas the master generates an extra acknowledge-related clock pulse (see Figure 6). A slave receiver which is addressed is obliged to generate an acknowledge signal after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges transmissions has to pull down the SDA line during the acknowledge clock pulse in such a way, that the SDA line is a stable low during the high period of the acknowledge-related clock pulse. The setup and hold times must be taken into account. A master receiver must signal an end of transmitted data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line high to enable the master to generate the Stop condition. Figure 6. Acknowledgement sequence
CLOCK PULSE FOR ACKNOWLEDGEMENT 1 2 8 9
START SCL FROM MASTER
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
9/27
Device operation
STVM100
2.2
Read mode
In READ mode, after the Start condition, the master sets the slave address (see Figure 7). Followed by the READ/WRITE Mode Control bit (R/W=1) and the Acknowledge bit, the value in DAC register will be transmitted and the master receiver will send an Acknowledge bit to the slave transmitter. Finally the Stop condition will terminate the READ operation. In READ mode, the valid data is the first 7 bits and the P bit (the eight bit) is don't care.
2.3
Write mode
In WRITE mode the master transmits to the STVM100 slave receiver. The bus protocol is shown in Figure 7. Following the Start condition and slave address, a logic '0' (R/W = 0) is placed on the bus to identify a WRITE operation. After the acknowledgement by the slave, the data will be transmitted to the slave with the 7-bit which indicates the data is valid as well as the eighth bit "P" for the register's identification. When P = 1, the DAC register is written to, and when P = 0, the EEPROM is written to (Programming). After receiving the data, the slave will generate an acknowledge signal, then a Stop condition will terminate the WRITE operation. STVM100 is pre-programmed with 80H in the EEPROM after manufacturing. A period of tW (see Table 8) is needed for EEPROM programming. During this period, the slave will not acknowledge any WRITE operation. The bit P values in both READ and WRITE modes are shown in Table 3. Figure 7. Read/write mode sequence
START 1 0 SLAVE ADDRESS 0 1 1 1 1 R/W A 6 5 4 3 2 1 0 P A STOP
SCL
SDA
1
0
0
1
1
1
1
R/W
A
6
5
4
3
2
1
0
P
A
START
STOP
AI12276_b
Table 3.
Bit P read and write mode values
Operation READ P-bit value X 1 WRITE 0 Description Don't care DAC register WRITE EEPROM WRITE (programming)
2.4
VDD power supply ramp-up
The ramp-up from 10% VDD to 90%VDD level should be achieved in less than or equal to 10ms to ensure that the EEPROM and power-on reset circuits are synchronized, and the correct value is read from the EEPROM.
10/27
STVM100
Application information
3
Application information
The STVM100 is a programmable VCOM calibrator for the TFT-LCD to remove flickers. It provides a digital I2C interface to control the sink current output. This output drives an external resistive voltage divider, which can then be applied to an external VCOM buffer. The highest and lowest VCOM value is determined by three resistors, R1, R2, and RSET. The connection is shown in Figure 8. The sink current from the STVM100 OUT pin is given in Equation 1. This current then flows through RSET. This current must be less than 120A (see ISET value in Table 7 on page 15). Figure 8. R1, R2, and RSET connection
AVDD AVDD AVDD
R1
STVM100
OUT SET RSET
+
IOUT R2 VCOM
-
AI12933
Equation 1 AV DD D+1 I OUT = ------------- ------------------------128 20 ( R SET ) Note: "D" is a user-selected value, an integer ranging from 0 to 127. The VCOM value can be obtained in Equation 2. Equation 2 R2 R1 D+1 V COM = -------------------- AV DD 1 - ------------- ------------------------- R1 + R2 128 20 ( R SET )
11/27
Application information
STVM100
If the user-selected value is 0 (zero scale), the minimum current is sunk. The maximum VCOM value is obtained in Equation 3. Equation 3 R2 R1 1 V COM ( max ) = -------------------- AV DD 1 - --------- ------------------------- 128 20 ( R SET ) R1 + R2 If the user-selected value is 127 (full scale), the maximum current is sunk and the minimum VCOM value is obtained in Equation 4. Equation 4 R2 R1 V COM ( min ) = -------------------- AV DD 1 - ------------------------- R1 + R2 20 ( R SET )
During operation, the VCOM(max) and VCOM(min) range is set, based on different TFT-LCD processes.The R1 value is given based on the acceptable power loss from the AVDD supply rail. Using Equation 3 and Equation 4, the R2 and RSET values can be calculated. If RSET is put into Equation 1 on page 11 and maximum IOUT 120A, then R1 should be increased.
12/27
STVM100
Maximum rating
4
Maximum rating
Stressing the device above the ratings listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4.
Symbol TSTG TSLD(1) TJ VOUT VDD AVDD VSET PDIS
Absolute maximum ratings
Parameter Storage temperature (VDD Off, AVDD Off) Lead solder temperature for 10 seconds Maximum junction temperature (plastic package) Output voltage (OUT pin to GND) VDD to GND AVDD input voltage to GND Output voltage (SET pin to GND) TDFN8 Power dissipation TSSOP8 0.53 W Value -55 to 150 260 150 -0.3 to 20 +5.5 -0.3 to 20 -0.3 to 5.5 2.66 Unit C C C V V V V W
1. Reflow at peak temperature of 255C to 260C for < 30 seconds (total thermal budget not to exceed 180C for between 90 to 150 seconds).
13/27
DC and AC parameters
STVM100
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 5, Operating and ac Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and AC measurement conditions
Parameter VDD supply voltage VDD EEPROM programming supply voltage AVDD reference voltage Ambient operating temperature (TA) Conditions 2.25 to 3.6 2.25 to 3.6 4.5 to 20 -40 to 85 Unit V V V C
Table 6.
Symbol Cb CSDA CS
Capacitances
Parameter(1)(2) Bus capacitive load Capacitance on SDA WP = 0 Capacitance on SCL WP = 1 22 pF Min Max 400 10 10 Unit pF pF pF
1. Effective capacitance measured with power supply at 3V. Sampled only, not 100% tested. 2. At 25C, f = 1MHz.
14/27
STVM100 Table 7.
Sym
DC and AC parameters DC and AC characteristics
Description Supply voltage VDD EEPROM programming supply voltage VDD supply current Analog supply voltage AVDD supply current SET voltage resolution SET differential nonlinearity Monotonic over temperature 7 1 2 8 Through RSET To GND, AVDD = 20V To GND, AVDD = 4.5V 10 2.25 20 8 VSET + 0.5V T = 25C to 55C 0.7VDD 0.3VDD 0.22VDD 15 At 3mA 25 35 0.4 <10 13 120 200 45 VDD = 2.6V to 3.6V VDD = 2.25V to 3.6V 4.5 4.5 Test Condition(1) Min 2.25 2.25 Typ Max 3.6 3.6 50 20 13 25 Unit V V A V V A Bits LSB LSB LSB A k k V/V s V mV V V V A V
IDD(2) AVDD IAVDD(3) SETVR SETDN
SETZSE SET zero scale error SETFSE SET full scale error ISET(4) SETER SET current SET external resistance
AVDD to AVDD to SET voltage SET attenuation(5) OUTST VOUT SETVD VIH VIL OUT settling time OUT voltage SET voltage drift(5) SDA, SCL, WP input logic high SDA, SCL, WP input logic low SDA, SCL hysteresis(5) IIL(WPN) VOL(s) WPN input current SDA, SCL output logic low
1. Valid for ambient operating temperature: TA = -40 to 85C; VDD = 3V; AVDD = 10V; typical TA = 25C; OUT = 1/2AVDD; RSET = 24.9k (except where noted). 2. Simulated maximum current draw when Programming EEPROM is 23mA; should be considered when designing a power supply. 3. Tested at AVDD = 20V. 4. A typical Current of 20A is calculated using AVDD = 10V and RSET = 24.9k. The maximum suggested SET current should be 120A. 5. Simulated and determined via design and NOT directly tested.
15/27
DC and AC parameters Figure 9. Bus timing requirements sequence
STVM100
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:ST tF tHD:STA
AI00589
Table 8.
Sym fSCL tLOW tHIGH tSU:DAT tHD:DAT tR tF tBUF tDSP tSU:STA tHD:STA tSU:STO tW
AC characteristics
Description SCL clock frequency Clock low period Clock high period Data setup time Data hold time SDA and SCL rise time SDA and SCL fall time Bus free time before new transmission can start I2C spike rejection filter pulse width Repeated start condition setup time Repeated start condition hold time Stop condition setup time WRITE cycle time Dependent on load (see Table 6 on page 14) 1.3 Test Condition(1) Min 0 1.3 0.6 100 0 20 + 0.1Cb 900 300 300 Typ Max 400 Unit kHz s s ns ns ns ns s
0 0.6 0.6 0.6
50
ns s s s
100
ms
1. Valid for ambient operating temperature: TA = -40 to 85C; VDD = 3.0V to 3.6V; AVDD = 10V; OUT = 1/2AVDD; RSET = 24.9k (except where noted, see Figure 9).
16/27
STVM100
Typical operating characteristics
6
Typical operating characteristics
Typical operating characteristics for the STVM100 are TA = 25C, VDD = 3V, AVDD = 10V, OUT = 1/2AVDD, and RSET = 24.9k except where noted. Figure 10. VDD supply current v's VDD
27.5 27 26.5 IDD (A) 26 25.5 25 24.5 24 .2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VDD (V)
AI13362
Figure 11. AVDD supply current v's AVDD
10 9 8 7 IAVDD (A) 6 5 4 3 2 1 0 4.5 6 7.5 9 10.5 12 13.5 15 16.5 18 19.5
AVDD (V)
AI13363
17/27
Typical operating characteristics Figure 12. VDD supply current v's temperature
35
STVM100
30
IDD (A)
25
20
15 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TemperatureC
AI13364
Figure 13. AVDD supply current v's temperature
4.95 4.9 4.85 IAVDD (A) 4.8 4.75 4.7 4.65 4.6 4.55 4.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TemperatureC
AI13365
18/27
STVM100
Typical operating characteristics Figure 14. IOUT error v's temperature (STVM100 at middle scale)
0.06 0.05 0.04 IOUT error (LSB) 0.03 0.02 0.01 0 -40 -20 0 20 40 60 80 TemperatureC
AI13366
Figure 15. Total unadjusted error v's DAC setting
0.022474 Total unadjusted error (LSB) 0.020395 0.018316 0.016237 0.014158 0.012079 0.01 1 17 33 49 65 81 97 113 DAC settling (decimal)
AI13367
19/27
Typical operating characteristics Figure 16. Differential non-linearity v's DAC setting
STVM100
0.2 0.15 Differential non-linearity (LSB) 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 1 17 33 49 65 81 97 113 DAC setting (decimal)
AI13368
Figure 17. Integral non-linearity v's DAC setting
0.3 Integrate non-linearity (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3 1 17 33 49 65 81 97 113 DAC setting (decimal)
AI13369
20/27
STVM100 Figure 18. AVDD power-up response
Typical operating characteristics
AVDD VDD
VOUT VSET
ai13370
5ms/DIV AVDD: 5V/DIV, VDD: 5V/DIV, VOUT: 1V/DIV, VSET: 1V/DIV Figure 19. Full scale-up response
SCL
SDA
VOUT
VSET
ai13371
20s/DIV SCL: 5V/DIV, SDA: 5V/DIV, VOUT: 1V/DIV, VSET: 1V/DIV
21/27
Typical operating characteristics Figure 20. Full scale-down response
STVM100
SCL
SDA
VOUT
VSET
ai13372
20s/DIV SCL: 5V/DIV, SDA: 5V/DIV, VOUT: 1V/DIV, VSET: 1V/DIV
22/27
STVM100
Package mechanical
7
Package mechanical
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 21. MLPD-DFN 3 x 3 x.75mm, pitch 0.65, package mechanical data
D D2 1
L
E E2
8 e A3 A1
0.08 EZ_ME
A
b
1. Drawing is not to scale.
Table 9.
Sym
MLPD-DFN 3 x 3 x .75mm, pitch 0.65, package mechanical data
mm Typ Min 0.70 0.00 Max 0.80 0.05 Typ 0.0295 0.0008 0.0079 0.25 0.35 0.0118 0.1181 2.23 2.48 0.0937 0.1181 1.49 - 0.30 1.74 - 0.50 0.0646 0.0256 0.0157 0.0587 - 0.0118 0.0685 - 0.0197 0.0878 0.0976 0.0098 0.0138 inches Min 0.0276 0.0000 Max 0.0315 0.0020
A A1 A3 b D D2 E E2 e L
0.75 0.02 0.20 0.30 3.00 2.38 3.00 1.64 0.65 0.40
23/27
Package mechanical
STVM100
Figure 22. TSSOP8 - 8-lead, thin shrink small outline, 3mm x 3mm, mech. data
D
8
5 E1 E
c
1
4
A1 A CP b e A2
L L1
TSSOP8BM
Note:
Drawing is not to scale. Table 10.
Sym Typ A A1 A2 b c CP D e E E1 L L1 N 3.000 0.650 4.900 3.000 0.550 0.950 0 8 6 2.900 - 4.6500 2.900 0.400 0.850 0.050 0.750 0.250 0.130 Min Max 1.100 0.150 0.950 0.400 0.230 0.100 3.100 - 5.150 3.100 0.700 0.1181 0.0256 0.1929 0.1181 0.0217 0.0374 0 8 6 0.1142 - 0.1831 0.1142 0.0157 0.0335 0.0020 0.0295 0.0098 0.0051 Typ Min Max 0.0433 0.0059 0.0374 0.0157 0.0091 0.0039 0.1220 - 0.2028 0.1220 0.0276
TSSOP8 - 8-lead, thin shrink small outline, 3mm x 3mm, mech. data
mm inches
24/27
STVM100
Part numbering
8
Part numbering
Table 11.
Example:
Ordering information scheme
STVM100 DC 6 F
Device type STVM100, VCOM calibrator with 7-bit DAC and I2C interface
Package DC = TDFN8 DS = TSSOP8
Temperature range 6 = -40 to 85C
Shipping method E = ECOPACK package, tubes F = ECOPACK package, tape & reel
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
25/27
Revision history
STVM100
9
Revision history
Table 12.
Date 09-May-2006 14-Jul-2006
Revision history
Revision 1 2 Initial release. Graphical and textual updates Document status upgraded to Preliminary Data; changed the wording of Input function to include `WRITE operations' instead of `programming' in Table 2: Pin names and functions; deleted some bracketed text and modified the P bit function in Section 2.2: Read mode; ensured that all of Equation 2 and Equation 3 were visible; amalgamated 2 cells containing the same information (VDD) in Table 7: DC and AC characteristics; deleted footnotes 2 and 3 of Table 8: AC characteristics; updated package mechanical information in Figure 21, Table 9, and Table 10. Reformatted Inside Cover Page according to new template; renamed section 1 Device overview and section 2 Device operation; deleted Signal names table; moved and renamed Table 2: Pin names and functions, addedSection 6: Typical operating characteristics and Figure 10 to Figure 20. Value added in Section 2.3: Write mode. Document status upgraded to full datasheet. Changes
08-Nov-2006
3
12-Feb-2007
4
20-Apr-2007 24-Jul-2007
5 6
26/27
STVM100
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
(c) 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
27/27

▲Up To Search▲

Price & Availability of STVM100DS6F

	To Download STVM100DS6F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .